<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Bahubalindruni, P.G.a c</style></author><author><style face="normal" font="default" size="100%">Goes, J.b</style></author><author><style face="normal" font="default" size="100%">Barquinha, P.c</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs</style></title><secondary-title><style face="normal" font="default" size="100%">2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">65 nm CMOS technologies</style></keyword><keyword><style  face="normal" font="default" size="100%">Amplification</style></keyword><keyword><style  face="normal" font="default" size="100%">Amplifiers (electronic)</style></keyword><keyword><style  face="normal" font="default" size="100%">High gain</style></keyword><keyword><style  face="normal" font="default" size="100%">High Speed</style></keyword><keyword><style  face="normal" font="default" size="100%">Industrial requirements</style></keyword><keyword><style  face="normal" font="default" size="100%">Integrated circuit manufacture</style></keyword><keyword><style  face="normal" font="default" size="100%">Operating frequency</style></keyword><keyword><style  face="normal" font="default" size="100%">Parametric amplification</style></keyword><keyword><style  face="normal" font="default" size="100%">Parametric amplifiers</style></keyword><keyword><style  face="normal" font="default" size="100%">Pipeline ADCs</style></keyword><keyword><style  face="normal" font="default" size="100%">Pipelines</style></keyword><keyword><style  face="normal" font="default" size="100%">Reconfigurable hardware</style></keyword><keyword><style  face="normal" font="default" size="100%">Residue amplification</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2016</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983780977&amp;doi=10.1109%2fSMACD.2016.7520732&amp;partnerID=40&amp;md5=d1a0c7ec842a6ada7cc03638a6c993df</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">Institute of Electrical and Electronics Engineers Inc.</style></publisher><isbn><style face="normal" font="default" size="100%">9781509004904</style></isbn><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology. © 2016 IEEE.</style></abstract><notes><style face="normal" font="default" size="100%">cited By 0; Conference of 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 ; Conference Date: 27 June 2016 Through 30 June 2016; Conference Code:123090</style></notes></record></records></xml>