<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Bahubalindruni, P.G.a c</style></author><author><style face="normal" font="default" size="100%">Tavares, V.G.b</style></author><author><style face="normal" font="default" size="100%">Fortunato, E.a</style></author><author><style face="normal" font="default" size="100%">Martins, R.a</style></author><author><style face="normal" font="default" size="100%">Barquinha, P.a</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Novel linear analog-adder using a-IGZO TFTs</style></title><secondary-title><style face="normal" font="default" size="100%">Proceedings - IEEE International Symposium on Circuits and Systems</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">Adders</style></keyword><keyword><style  face="normal" font="default" size="100%">Analog adder</style></keyword><keyword><style  face="normal" font="default" size="100%">Annealing temperatures</style></keyword><keyword><style  face="normal" font="default" size="100%">Circuit performance</style></keyword><keyword><style  face="normal" font="default" size="100%">Conventional approach</style></keyword><keyword><style  face="normal" font="default" size="100%">Flexible electronics</style></keyword><keyword><style  face="normal" font="default" size="100%">Fundamental frequencies</style></keyword><keyword><style  face="normal" font="default" size="100%">Igzo tfts</style></keyword><keyword><style  face="normal" font="default" size="100%">Linearization</style></keyword><keyword><style  face="normal" font="default" size="100%">Peak-to-peak values</style></keyword><keyword><style  face="normal" font="default" size="100%">Power supply voltage</style></keyword><keyword><style  face="normal" font="default" size="100%">Reconfigurable hardware</style></keyword><keyword><style  face="normal" font="default" size="100%">Semiconducting indium compounds</style></keyword><keyword><style  face="normal" font="default" size="100%">Substrates</style></keyword><keyword><style  face="normal" font="default" size="100%">Thin film transistors</style></keyword><keyword><style  face="normal" font="default" size="100%">Voltage measurement</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2016</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983450915&amp;doi=10.1109%2fISCAS.2016.7538993&amp;partnerID=40&amp;md5=2d5896eb6c6a87dc8d5cf1e05fc33e2f</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">Institute of Electrical and Electronics Engineers Inc.</style></publisher><volume><style face="normal" font="default" size="100%">2016-July</style></volume><pages><style face="normal" font="default" size="100%">2098-2101</style></pages><isbn><style face="normal" font="default" size="100%">9781479953400</style></isbn><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics. © 2016 IEEE.</style></abstract><notes><style face="normal" font="default" size="100%">cited By 0; Conference of 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference Date: 22 May 2016 Through 25 May 2016; Conference Code:123235</style></notes></record></records></xml>