<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Kiazadeh, A.a b</style></author><author><style face="normal" font="default" size="100%">Gomes, H.L.b c</style></author><author><style face="normal" font="default" size="100%">Barquinha, P.a</style></author><author><style face="normal" font="default" size="100%">Martins, J.a</style></author><author><style face="normal" font="default" size="100%">Rovisco, A.a</style></author><author><style face="normal" font="default" size="100%">Pinto, J.V.a</style></author><author><style face="normal" font="default" size="100%">Martins, R.a</style></author><author><style face="normal" font="default" size="100%">Fortunato, E.a</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors</style></title><secondary-title><style face="normal" font="default" size="100%">Applied Physics Letters</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">Bias voltage</style></keyword><keyword><style  face="normal" font="default" size="100%">Coatings</style></keyword><keyword><style  face="normal" font="default" size="100%">Electrical performance</style></keyword><keyword><style  face="normal" font="default" size="100%">Encapsulation layer</style></keyword><keyword><style  face="normal" font="default" size="100%">Indium</style></keyword><keyword><style  face="normal" font="default" size="100%">Indium gallium zinc oxides</style></keyword><keyword><style  face="normal" font="default" size="100%">Neutralization process</style></keyword><keyword><style  face="normal" font="default" size="100%">Operational stability</style></keyword><keyword><style  face="normal" font="default" size="100%">Passivation</style></keyword><keyword><style  face="normal" font="default" size="100%">Semi-conductor surfaces</style></keyword><keyword><style  face="normal" font="default" size="100%">Stability</style></keyword><keyword><style  face="normal" font="default" size="100%">Stretched exponential models</style></keyword><keyword><style  face="normal" font="default" size="100%">Surface defects</style></keyword><keyword><style  face="normal" font="default" size="100%">Thin film transistors</style></keyword><keyword><style  face="normal" font="default" size="100%">Threshold voltage</style></keyword><keyword><style  face="normal" font="default" size="100%">Threshold voltage shifts</style></keyword><keyword><style  face="normal" font="default" size="100%">Transistors</style></keyword><keyword><style  face="normal" font="default" size="100%">Zinc coatings</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2016</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://www.scopus.com/inward/record.uri?eid=2-s2.0-84981155175&amp;doi=10.1063%2f1.4960200&amp;partnerID=40&amp;md5=d3f5245134d17c2b45d10c6623cb25ef</style></url></web-urls></urls><number><style face="normal" font="default" size="100%">5</style></number><publisher><style face="normal" font="default" size="100%">American Institute of Physics Inc.</style></publisher><volume><style face="normal" font="default" size="100%">109</style></volume><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons. © 2016 Author(s).</style></abstract><notes><style face="normal" font="default" size="100%">cited By 0</style></notes></record></records></xml>